This invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory device having a number of memory cells.
Conventional dynamic random access memory devices employ one-transistor type memory cells each including a MOS transistor and capacitor. However, there are certain undesirable characteristics of MOS transistors, primary in regard to their size limitation. A cell area is occupied by one MOS transistor including at least three regions; e.g., source, channel and drain regions. Accordingly, it is difficult to increase the memory cell density of the one-transistor type D-ROM without a great reduction of its permissible voltage. With a reduced power source voltage, however, the sub-threshold characteristic curve has a gentle slope, resulting in a dynamic random access memory device which is subjective to leak and exhibits low reliability.